A serial digital-to-analog converter (serial DAC) of known type is shown in FIG. 1 of the drawings. This serial DAC comprises a serial in, parallel out shift register 10 composed of D flip-flops 12 and 14 connected in series. Serial data is applied to the D and D input terminals of the flip-flop 12, and the Q and Q output of the flip-flop 12 are connected to the D and D inputs of the flip-flop 14. Clock signals are applied to the respective clock terminals of the flip-flops. Thus, as a stream of serial data is applied to the data input terminals of the flip-flop 12, and clock pulses are applied to the clock terminals of the flip-flops, the data is made available sequentially at the data output terminals of the flip-flops.
The output terminals of the flip-flops 12 and 14 are connected to respective current switches 16 and 18. Each switch comprises a differential amplifier composed of two NPN transistors connected in common emitter configuration. The switches supply differential current I.sub.out to their output terminals, which are connected together. The input terminals of the switches 16 and 18 are connected to respective constant current sources 20 and 22. The current source 22 supplies twice the current supplied by the source 20.
If, for example, the sequence of binary digits indicated in the top row of Table I was applied to the input of the flip-flop 12, and a clock transition was applied to the clock inputs for each occurrence of the numeral 1 in the second row of the table, the Q outputs of the flip-flops 12 and 14 would respond to the clock transition by entering the states indicated in the third and fourth rows of the table. The output current I.sub.out would have the value indicated in the fourth row of Table I.
TABLE I __________________________________________________________________________ Data In 1 0 0 0 0 1 1 0 0 0 1 * CLK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Q.sub.12 1 0 0 0 0 1 1 0 0 0 1 * Q.sub.14 * 1 0 0 0 0 1 1 0 1 0 1 I.sub.out * I 0 0 0 I/2 3I/2 I 0 0 I/2 * __________________________________________________________________________
This type of serial DAC may be used in an analog-to-digital converter (ADC), where a digital pseudo random bit sequence is converted to analog form and summed with an analog signal for noise dithering.
A disadvantage of the DAC shown in FIG. 1 is that the switch 12 can take up to twice as long to settle as the switch 16, because it has to switch twice the current. (The settling time of the switch 16 or 18 may be defined as the time that elapses from the clock transition until the output current is within a specified percentage of its final value.) Moreover, assuming that the output drive capabilities of the flip-flops 12 and 14 are equal, the flip-flop 14 will take longer to settle in response to a change in its output signal because of the higher capacitive loading owing to the higher current being switched. Even if the current switches are much faster than the flip-flops, there may be parasitic currents proportional to the flip-flop output. Consequently, the MSB stage, comprising the flip-flop 14 and the current switch 18, takes substantially longer to settle than lower order stages, and this imposes a limit on the rate at which data can be applied to the DAC and accurately converted.